1. Field of the Invention
The present invention relates to a semiconductor testing equipment for testing semiconductor devices, and particularly to a programmable load circuit that serves as the load of a device under test.
2. Description of the Related Art
Electronic circuits which are used exclusively for testing of input/output pins of a device under test (hereinbelow referred as "DUT") and which are provided on the test head of semiconductor testing devices are referred to as "pin electronics." Pin electronics comprise a driver for impressing a prescribed signal to the pin of a DUT, a comparator for judging whether the signal outputted from the DUT is high level or low level, and a programmable load circuit that becomes the load when a signal is outputted from the DUT.
Programmable load circuits allow alteration of the load conditions by means of a processing device that controls the entire semiconductor testing device, and can produce the load prescribed in the specifications of a DUT.
FIG. 1 shows the circuits making up a programmable load circuit of the prior art.
In FIG. 1, the pin electronics are made up of driver 3, comparator 4, and programmable load circuit 100, to which DUT 2 is connected to perform testing.
Programmable load circuit 100 includes: diode bridge 107 made up of four diodes D21-D24; first current source 104 and second current source 105 that serve as loads of the DUT; programmable voltage source 106 that impresses to diode bridge 107 a threshold voltage Vth used for judgment when selecting one of first current source 104 and second current source 105, which are the loads; transistors Q25-Q28 that serve as switches connecting first current source 104 and second current source 105 to diode bridge 107 or to the ground potential; ON/OFF signal source 101 that outputs a signal for effecting ON/OFF control of programmable load circuit 100; and first level-shift circuit 102 and second level-shift circuit 103 that drive transistors Q25-Q28 according to the output signal of ON/OFF signal source 101.
The ON state of programmable load circuit 100 is the state in which DUT 2 is connected to first current source 104 and second current source 105, which are the loads, and the OFF state of programmable load circuit 100 is the state in which first current source 104 and second current source 105 are each connected to the ground potential and load is not connected to DUT 2.
Here, output voltage Vth of programmable voltage source 106, output current I.sub.11 of first current source 104, and output current I.sub.12 Of second current source 105 can each be individually changed and set to a prescribed value by a programming process.
The operation of a prior-art programmable load circuit of this configuration will next be explained based on FIG. 2 with reference to FIG. 1.
In addition, the explanation of operation will be based on the following conditions:
1: Output voltage of DUT 2; low level=0 V, high level=3 V PA1 2: Output voltage of driver 3; low level=0 V, high level=3 V PA1 3: Threshold voltage Vth=1.5 V PA1 4: Forward voltage of diodes D21-D24 V.sub.F =0.7 V PA1 is a programmable load circuit that is provided in a semiconductor testing equipment and that becomes the load during output of a device under test including: PA1 a first current source; PA1 a second current source; PA1 a diode bridge to which is impressed a threshold voltage for selecting either one of the first current source or the second current source as load, and which is connected to input/output pins of the device under test; PA1 a first switch that connects the first current source and the diode bridge; PA1 a second switch that connects the second current source and the diode bridge; PA1 a first constant-voltage source for discharging electric charge accumulated in the parasitic capacitance of the first node, which is the connecting portion of the diode bridge and the first switch; PA1 a second constant-voltage source for charging the parasitic capacitance of the second node, which is the connecting portion of the diode bridge and the second switch; PA1 a third switch that connects the first constant-voltage source and the first node; PA1 a fourth switch that connects the second constant-voltage source and the second node; and PA1 a control circuit which, when a signal is outputted from the device under test, turns ON the first switch and the second switch and turns OFF the third switch and the fourth switch and, when the device under test is in a signal-inputting state, turns OFF the first switch and the second switch and turns ON the third switch and the fourth switch. PA1 the third switch may be constituted by a first diode for clamping the voltage of the first node at the voltage of the first constant-voltage source; and PA1 the fourth switch may be constituted by a second diode for clamping the voltage of the second node at the voltage of the second-constant-voltage source. PA1 a third current source for pulling in the voltage of the second node to the output voltage of the second constant-voltage source when the device under test is in a signal-inputting state; PA1 a fourth current source for pulling in the voltage of the first node to the output voltage of the first constant-voltage source when the device under test is in a signal-inputting state; PA1 a first transistor for connecting the third current source to the second node; PA1 a second transistor for connecting the third current source to the ground potential; PA1 a third transistor for connecting the fourth current source to the first node; PA1 a fourth transistor for connecting the fourth current source to the ground potential; PA1 a first level-shift circuit that, when a signal is outputted from the device under test, turns the first transistor OFF and turns the second transistor ON; and when the device under test is in a signal-inputting state, turns the first transistor ON and turns the second transistor OFF; and PA1 a second level-shift circuit that, when a signal is outputted from the device under test, turns the third transistor OFF and turns the fourth transistor ON; and when the device under test is in a signal-inputting state, turns the third transistor ON and turns the fourth transistor OFF. PA1 the fourth switch may be constituted by a second p-channel MOS transistor and a second n-channel MOS transistor, the sources and drains of these two transistors being mutually connected. PA1 a first driver circuit, for driving the third switch, provided with: a third p-channel MOS transistor having its source connected to the positive voltage source, its drain connected to the gate of the first n-channel MOS transistor, and its gate connected to the gate of the first p-channel MOS transistor; and a third n-channel MOS transistor having its drain connected to the drain of the third p-channel MOS transistor, its source connected to the negative voltage source, and its gate connected to the gate of the first p-channel MOS transistor; PA1 and a second driver circuit, for driving the fourth switch, provided with a fourth p-channel MOS transistor having its source connected to the positive voltage source, its drain connected to the gate of the second n-channel MOS transistor, and its gate connected to gate of the second p-channel MOS transistor; and a fourth n-channel MOS transistor having its drain connected to the drain of the fourth p-channel MOS transistor, its source connected to the negative voltage source, and its gate connected to the gate of the second p-channel MOS transistor. PA1 the fourth switch may be constituted by a second diode bridge. PA1 a first driver circuit, for driving the third switch, provided with: a third current source and a fourth current source that determine the current that flows to the first diode bridge; a first transistor that connects the third current source to the first diode bridge; a second transistor that connects the third current source to the ground potential; a third transistor that connects the fourth current source to the first diode bridge; a fourth transistor that connects the fourth current source to the ground potential; a first level-shift circuit that, when the third switch is turned ON, turns ON the first transistor and turns OFF the second transistor, and when the third switch is turned OFF, turns OFF the first transistor and turns ON the second transistor; a second level-shift circuit that, when the third switch is turned ON, turns ON the third transistor and turns OFF the fourth transistor, and when the third switch is turned OFF, turns OFF the third transistor and turns ON the fourth transistor; PA1 and a second driver circuit, for driving the fourth switch, provided with: a fifth current source and a sixth current source that determine the current that flows to the second diode bridge; a fifth transistor that connects the fifth current source to the second diode bridge; a sixth transistor that connects the fifth current source to the ground potential; a seventh transistor that connects the sixth current source to the second diode bridge; an eighth transistor that connects the sixth current source to the ground potential; a third level-shift circuit that, when the fourth switch is turned ON, turns ON the fifth transistor and turns OFF the sixth transistor, and when the fourth switch is turned OFF, turns OFF the fifth transistor and turns ON the sixth transistor; and a fourth level-shift circuit that, when the fourth switch is turned ON, turns ON the seventh transistor and turns OFF the eighth transistor, and when the fourth switch is turned OFF, turns OFF the seventh transistor and turns ON the eighth transistor.
Under the above-described conditions, when a signal is outputted from DUT 2, the output of driver 3 is maintained in a high-impedance (HiZ) state and programmable load circuit 100 is set to ON. The ON/OFF control of programmable circuit 100 is effected by the output signal of ON/OFF signal source 101, and programmable load circuit 100 turns ON when a high-level signal is outputted from ON/OFF signal source 101.
When a high-level signal is outputted from ON/OFF signal source 101, first level-shift circuit 102 supplies a base current only to transistor Q26, and second level-shift circuit 103 supplies a base current only to transistor Q28. At this time, both transistors Q26 and Q28 are ON, and both transistors Q25 and Q27 are OFF.
If a high level (3 V) is outputted from DUT 2 in this state, current I.sub.12 flows from DUT 2 to second current source 105 by way of diode D24, because the output voltage of DUT 2 is a higher voltage than threshold voltage Vth (1.5 V). On the other hand, if a low level (0 V) is outputted from DUT 2, current I.sub.11 flows from first current source 104 to DUT 2 via diode D22 because the output voltage of DUT 2 is a lower voltage than threshold voltage Vth (1.5 V).
Thus, load connected to the output of DUT 2 is switched in accordance with its output voltage, and the load value is determined by current value I.sub.11 of first current source 104 and current value I.sub.12 of second current source 105.
Moreover, as explained hereinabove, because the output value of each of programmable voltage source 106, first current source 104, and second current source 105 can be changed by a programming process, current values I.sub.11 and I.sub.12, which become load, can be changed in accordance with the specifications of DUT 2.
On the other hand, when a signal is not outputted from DUT 2, i.e., in a case in which DUT 2 is in a signal-inputting state, a signal is outputted from driver 3 to DUT 2 and the output of DUT 2 is set to a high-impedance state (HiZ). In addition, because load need not be connected, programmable load circuit 100 is set to OFF.
Programmable load circuit 100 turns OFF in a case in which a low-level signal is outputted from ON/OFF signal source 101. When a low-level signal is outputted from ON/OFF signal source 101, first level-shift circuit 102 supplies a base current only to transistor Q25 and second level-shift circuit 103 supplies a base current only to transistor Q27. At this time, both transistors Q25 and Q27 turn ON and both transistors Q26 and Q28 turn OFF.
When both transistors Q25 and Q27 are ON, first current source 104 is connected to the ground potential by way of transistor Q25, and second current source 105 is connected to the ground potential by way of transistor Q27. As a result, first current source 104 and second current source 105 do not function as load of DUT 2.
However, when programmable load circuit 100 is switched from ON to OFF, transistors Q26 and Q28 switch from ON to OFF, whereby, as shown in FIG. 2, the voltage of node A is discharged at a time constant due to the parasitic capacitance held in diodes D21 and D22 and transistor Q26 and changes to 0 V; and the voltage of node B is charged at time constant due to the parasitic capacitance held in diodes D23 and D24 and transistor Q28 and changes to threshold voltage Vth (1.5 V).
Subsequently, when the output signal of driver 3 switches from the low level (0 V) to the high level (3 V), the voltage of node B is pulled toward the voltage of node C and changes from threshold voltage Vth (1.5 V) to 3 V, while node A is maintained at 0 V.
In a programmable load circuit of the prior art as described hereinabove, there is the drawback that when the DUT is driven by the driver, the rise time of the output current is retarded by the programmable load circuit.
Even if the programmable load circuit is OFF, the output of the driver is still connected to the diode bridge of the programmable load circuit. Moreover, the parasitic capacitance existing in each of node A and node B becomes load of driver.
As an example, when the programmable load circuit is OFF and the output of the driver is switched from low level=0 V to high level=3 V, the parasitic capacitance of node B is charged, and as a result, the rise time of the output waveform of the driver (node C) is retarded by a time Dt, as shown in the timing chart of FIG. 2.